The subject invention is directed generally to boundary scan circuitry, and more particularly to boundary scan circuitry that configures the inputs and outputs of the associated device to be bi-directional for boundary scan test purposes.
Boundary scan testing is commonly utilized to test the interconnections between digital devices that comprise a system, where the interconnected devices can include integrated circuits, application specific integrated circuits (ASICs), hybrids, and circuit boards, for example. For boundary scan test capability, a device includes scan circuits that are capable of isolating device I/O pins from the interior logic of the device and directly accessing such I/O pins, which allows special interconnection test patterns to be applied and observed without interference from the interior logic functions.
Boundary scan test capability is commonly implemented with boundary scan cells respectively associated with those I/O pins for which boundary scan testing capability is being provided, with each boundary scan cell containing a scan flip-flop. The scan flip-flops are arranged into a register chain that is capable of operation in serial and parallel modes, so that test patterns can be loaded serially, applied in parallel, and test results can be read out serially.
For testing, special interconnection test patterns are serially loaded into scan flip-flops for output pins. After a test pattern is loaded, the output scan cells containing the test pattern are switched to drive the output pins associated with the scan chain registers in accordance with the test pattern. Subsequently, the signals observed on input pins are stored in associated scan flip-flops. The stored inputs are then serially read out to evaluate the test. A further test pattern can be serially loaded in scan flip-flops while stored inputs are being serially read out.
Boundary scan test patterns are basically designed to achieve the following:
1. To drive each device output to the high state and to the low state at different times. Proper reception at the appropriate inputs verifies continuity.
2. To drive each device output to the state opposite that of all other outputs, for both the low state and the high state. A short circuit between two or more outputs will be indicated by contention between the shorted drivers.
The paper "INTERCONNECT TESTING WITH BOUNDARY SCAN," Wagner, IEEE Proc. 1987 International Test Conference, pages 52-57 generally describes the application and implementation of boundary scan testing, and test patterns that allow for efficient boundary scan testing.
A consideration with known boundary scan circuits is the requirement that the specific input/output functions of device pins must be known (i.e., which pins are inputs, which are outputs, and which are bidirectional), and therefore test patterns must be configured to the specific I/O functions of the interconnected devices.
A further consideration with known boundary scan circuits is the inability to distinguish between interconnect failures and failure of device I/O buffers.